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FEATURES High Speed 250 MHz -3 dB Bandwidth (G = +1) 3000 V/ s Slew Rate 21 ns Settling Time to 0.1% 1.8 ns Rise Time for 2 V Step Low Power 3.5 mA/Amp Power Supply Current (35 mW/Amp) Single Supply Operation Fully Specified for +5 V Supply Good Video Specifications (RL = 150 , G = +2) Gain Flatness 0.1 dB to 30 MHz 0.04% Differential Gain Error 0.10 Differential Phase Error Low Distortion -78 dBc THD at 5 MHz -61 dBc THD at 20 MHz High Output Current of 50 mA Available in a 14-Lead Plastic DIP and SOIC APPLICATIONS Image Scanners Active Filters Video Switchers Special Effects PRODUCT DESCRIPTION
Quad 3000 V/ s, 35 mW Current Feedback Amplifier AD8004
CONNECTION DIAGRAM Plastic DIP (N) and SOIC (R) Packages
OUTPUT 1 -IN 2 +IN 3 +VS 4 +IN 5 -IN 6 OUTPUT 7 2 3 1 4 14 OUTPUT 13 -IN 12 +IN
AD8004
(TOP VIEW)
11 -VS 10 +IN 9 -IN 8 OUTPUT
30 MHz while offering differential gain and phase error of 0.04% and 0.10. This makes the AD8004 suitable for video electronics such as cameras and video switchers. The AD8004 offers low power of 3.5 mA/amplifier and can run on a single +4 V to +12 V power supply, while being capable of delivering up to 50 mA of load current. All this is offered in a small 14-lead plastic DIP or 14-lead SOIC package. These features make this amplifier ideal for portable and battery powered applications where size and power are critical. The outstanding bandwidth of 250 MHz along with 3000 V/s of slew rate make the AD8004 useful in many general purpose, high speed applications where dual power supplies of up to 6 V and single supplies from 4 V to 12 V are needed. The AD8004 is available in the industrial temperature range of -40C to +85C.
0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 1ST 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 1ST 2ND 3RD 4TH 5TH 6TH 7TH DIFF PHASE - Degrees 2ND 3RD 4TH 5TH 6TH 7TH
The AD8004 is a quad, low power, high speed amplifier designed to operate on single or dual supplies. It utilizes a current feedback architecture and features high slew rate of 3000 V/s making the AD8004 ideal for handling large amplitude pulses. Additionally, the AD8004 provides gain flatness of 0.1 dB to
+1
NORMALIZED FREQUENCY RESPONSE - dB
0 G = +2 VIN = 50mV rms RL = 100 RF = 1.10k R PACKAGE -1 5VS +5VS -3 -4 +5VS 5VS -5 -6 -7 -8 1 10 40 FREQUENCY - MHz 100 -9 500 -2
DIFF GAIN - %
NORMALIZED FLATNESS - dB
+0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
80 IRE RL = 150 VS = 5V RF = 1.21k 8TH 9TH 10TH 11TH
80 IRE RL = 150 VS = 5V RF = 1.21k 8TH 9TH 10TH 11TH
Figure 1. Frequency Response and Flatness, G = +2
Figure 2. Differential Gain/Differential Phase
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD8004-SPECIFICATIONS (@ T = + 25 C, V =
A S
5 V, RL = 100
, unless otherwise noted)
Min AD8004A Typ Max 185
250
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth, N Package
Bandwidth for 0.1 dB Flatness
Conditions G = +2, RF = 698 G = +1, RF = 806 G = +2 G = +2, VO = 4 V Step G = -2, VO = 4 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 k f = 5 MHz, G = +2, RL = 1 k f = 5 MHz, G = +2, RL = 1 k f = 10 kHz f = 10 kHz, +In -In NTSC, G = +2, R L = 150 , RF = 1.21 k NTSC, G = +2, R L = 150 , RF = 1.21 k NTSC, G = +2, RL = 1 k, R F = 1.21 k NTSC, G = +2, RL = 1 k, R F = 1.21 k
Units MHz
MHz
Slew Rate Settling Time to 0.1% Rise & Fall Time (10% to 90%) NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, R Package, Worst Case Crosstalk, N Package, Worst Case Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage
30 3000 2000 21 1.8 -78 -69 -64 1.5 38 38 0.04 0.10 0.01 0.04 1.0 1.5 15 35 40 3.5 5 90 110 110 120
MHz V/s V/s ns ns dBc dB dB nV/Hz pA/Hz pA/Hz % Degree % Degree mV mV V/C A A A A k k M pF V dB A/V A/V V mA mA 6.0 17 20 V mA mA dB A/V A/V
TMIN-TMAX Offset Drift -Input Bias Current TMIN-TMAX +Input Bias Current Open-Loop Transresistance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage -Input Current +Input Current OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Operating Range Total Quiescent Current Power Supply Rejection Ratio -Input Current +Input Current
Specifications subject to change without notice.
TMIN-TMAX VO = 2.5 V TMIN-TMAX +Input -Input +Input VCM = 2.5 V VCM = 2.5 V, TMIN-TMAX VCM = 2.5 V, TMIN-TMAX R L = 150
170
290 220 2 50 1.5 3.2
52
58 1 12 3.9 50 180
100 2.0 TMIN-TMAX VS = 2 V TMIN-TMAX TMIN-TMAX 56
14 16 62 0.5 4
-2-
REV. B
(@ TA = + 25 C, VS = +5 V, RL = 100
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth, N Package
Bandwidth for 0.1 dB Flatness
, unless otherwise noted)
Conditions G = +2, RF = 698 G = +1, RF = 806 G = +2 G = +2, VO = 2 V Step G = +2, VO = 2 V Step G = +2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 k f = 5 MHz, G = +2, RL = 1 k f = 5 MHz, G = +2, RL = 1 k f = 10 kHz f = 10 kHz, +In -In NTSC, G = +2, R L = 150 , RF = 1.21 k NTSC, G = +2, R L = 150 , RF = 1.21 k NTSC, G = +2, RL = 1 k, R F = 1.21 k NTSC, G = +2, RL = 1 k, R F = 1.21 k Min AD8004A Typ Max 150
200
AD8004
Units MHz
MHz
Slew Rate Settling Time to 0.1% Rise & Fall Time (10% to 90%) NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, R Package, Worst Case Crosstalk, N Package, Worst Case Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage
30 1100 24 2.3 -65 -69 -64 1.5 38 38 0.06 0.25 0.01 0.08 1.0 1 15 20 35 2.5 3 80 100 100 115
MHz V/s ns ns dBc dB dB nV/Hz pA/Hz pA/Hz % Degree % Degree mV mV V/C A A A A k k M pF V dB A/V A/V V mA mA V mA mA dB A/V A/V
TMIN-TMAX Offset Drift -Input Bias Current TMIN-TMAX +Input Bias Current Open Loop Transresistance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage -Input Current +Input Current OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Operating Range Total Quiescent Current Power Supply Rejection Ratio -Input Current +Input Current
Specifications subject to change without notice.
TMIN-TMAX VO = +1.5 V to +3.5 V TMIN-TMAX +Input -Input +Input
140
230 170 2 50 1.5 3.2
VCM = +1 V to +3 V VCM = +1 V to +3 V, TMIN -TMAX VCM = +1 V to +3 V, TMIN -TMAX R L = 150
52
57 2 15 0.9 to 4.1 50 95
0, +4 TMIN-TMAX VS = +1 V, VCM = +2.5 V TMIN -TMAX TMIN -TMAX 13 14.5 62 1 6
+12 14 15.5
56
REV. B
-3-
AD8004
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 Plastic DIP Package (N) . . . . . . . . . Observe Derating Curves Small Outline Package (R) . . . . . . . . Observe Derating Curves Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.5 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range (N, R) . . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . - 40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 14-Lead Plastic DIP Package: JA = 90C/W 14-Lead SOIC Package: JA = 140C/W
The maximum power that can be safely dissipated by the AD8004 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8004 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves (shown below in Figure 3).
2.0 TJ = +150 C 14-LEAD PLASTIC DIP PACKAGE 1.5
ORDERING GUIDE
Model AD8004AN AD8004AR-14 AD8004AR-14-REEL AD8004AR-14-REEL7 Temperature Range - 40C to +85C - 40C to +85C - 40C to +85C - 40C to +85C Package Description 14-Lead Plastic DIP 14-Lead SOIC 13" Tape and Reel 7" Tape and Reel Package Option N-14 R-14 R-14 R-14
MAXIMUM POWER DISSIPATION - Watts
1.0
14-LEAD SOIC PACKAGE 0.5
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C
80 90
Figure 3. Maximum Power Dissipation vs. Temperature
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8004 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
AD8004
604 604 50 SCOPE INPUT
VIN 249 61.9 499 50 SCOPE INPUT 50
50 VIN 50 0.1 F 0.1 F 10 F 10 F -VS
+VS
0.1 F 0.1 F 10 F 10 F
+VS
-VS
Figure 4. Test Circuit; Gain = +2
Figure 8. Test Circuit; Gain = -2
Figure 5.* 100 mV Step Response; G = +2, VS = 2.5 V or 5 V
Figure 9.* 100 mV Step Response; G = -2, VS = 2.5 V or 5 V
Figure 6.* Step Response; G = +2, VS = 5 V
+2
NORMALIZED FREQUENCY RESPONSE - dB
Figure 10.* Step Response; G = -2, VS = 5 V
+1 NORMALIZED FREQUENCY RESPONSE - dB 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 1 10 40 FREQUENCY - MHz 100 500 VS = 5V RF = 499 VIN = 50mV rms RL = 100 N PACKAGE G = -1
+1 0 -1 -2 -3 -4 -5 -6 -7 -8 1
G = +1, RF = 698
RL = 100 VIN = 50mV (G = +1, +2) VIN = 5mV (G = +10) G = +2, RF = 604
G = -2
G = -10
G = +10, RF = 499
10 40 FREQUENCY - MHz
100
500
Figure 7. Frequency Response; G = +1, +2, +10, VS = 5 V
*NOTE: VS = 2.5 V operation is identical to V S = +5 V single supply operation.
Figure 11. Frequency Response, G = -1, -2, -10
REV. B
-5-
AD8004
+9 +6 +3 1V rms
OUTPUT LEVEL - dBV
+3 1V rms 0 -3
OUTPUT LEVEL - dBV G =+2 VS = 5V RF = 604
0 -3 -6 -9 -12 -15 -18 -21 1 10 40 FREQUENCY - MHz 100 500
-6 -9 -12 -15 -18 -21 -24 -27 1 10 40 FREQUENCY - MHz 100 500 G = +2 VS = +5V RF = 604
Figure 12. Large Signal Frequency Response; VS = 5.0 V, G = +2, RF = 604
Figure 15. Large Signal Frequency Response; VS = +5.0 V, G = +2, RF = 604
-40 G = +2 VO = 2V p-p RF = 698 2ND RL = 150
-40 G = +2 VO = 2V p-p RF = 698 3RD RL = 1k 2ND RL = 150 3RD RL = 150
-50
-50
3RD RL = 150
DISTORTION - dBc
DISTORTION - dBc
-60
-60
-70
-70
-80 2ND RL = 1k 3RD RL = 1k
-80 2ND RL = 1k
-90
-90
-100
1 FREQUENCY - MHz
10
20
-100 1 FREQUENCY - MHz
10
20
Figure 13. Distortion vs. Frequency; VS = 5 V
Figure 16. Distortion vs. Frequency; VS = +5 V
+1
-10
NORMALIZED FREQUENCY RESPONSE - dB
604
0 G = +2 VIN = 50mV rms RL = 100 RF = 1.10k R PACKAGE -1 5VS +5VS -2 -3 -4 +5VS 5VS -5 -6 -7 -8 1 10 40 FREQUENCY - MHz 100 -9 500
-15
VIN
5VS
50 VOUT
604 154 154
-20 -25 CMRR - dB -30 -35 -40 -45 -50 -55
57.6
+5VS
NORMALIZED FLATNESS - dB
+0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
+5VS
5VS -60 0.03 0.1 1 10 FREQUENCY - MHz 100 500
Figure 14. Frequency Response and Flatness, G = +2
Figure 17. CMRR vs. Frequency; VS = 5 V or +5 V, VIN = 200 mV rms, Other Sides Are Equal, RTO
-6-
REV. B
AD8004
INPUT CURRENT NOISE - pA/ Hz
10 9 8 7 6 5 4 3 2
1000
0 -10 -20 -30 -40 -PSRR -50 -60 -70 -80 10k G = +2 5VS OR 2.5VS RF = 1k 100mV rms ON TOP OF dc BIAS +PSRR
500 300 200
INPUT VOLTAGE NOISE - nV/ Hz
10 9 8 7 6 5 4 3 2
100 + OR - INPUT CURRENT NOISE 70 50 40 30 VOLTAGE NOISE 20 10 1M
1
10
100
1k 10k FREQUENCY - Hz
100k
PSRR - dB
100k
1M 10M FREQUENCY - Hz
100M
500M
Figure 18. Noise vs. Frequency, VS = +5 V or 5 VS
Figure 21. PSRR vs. Frequency
-20
100 RbT = 50 5VS OR +5VS
CROSSTALK - dB
-30 -40 -50 -60 -70 -80 -90
10
IMPEDANCE -
G = +2 RF = 698 POWER = 0dBm (224mV rms)
G = +2 RF = 1.10k 5VS VIN = 200mV rms INPUT TO SIDE 1 RL1 = 1k R PACKAGE
OUTPUT = SIDE 2 OUTPUT = SIDE 4
1
+5VS
RbT = 0
OUTPUT = SIDE 3
0.1
5VS
-100 -110
0.01 0.03
0.1
1 10 FREQUENCY - MHz
100
500
-120 0.03
0.1
1 10 FREQUENCY - MHz
100
500
Figure 19. Output Impedance vs. Frequency
Figure 22. Crosstalk (Output to Output) vs. Frequency
110
0
GAIN
+60 +50
100 GAIN 90 80
GAIN - dB
0
PHASE - Degrees
90 PHASE -180
+40
GAIN - dB
+30 +20 +10
70 60 50 40 30 20
-100
-240
VIN = -40dBm VS = 5V
0 -10
-150
-360 0.03 0.1 1 10 FREQUENCY - MHz 100 500
10 100k
1M
10M FREQUENCY - Hz
100M
-200 1G
Figure 20. Open-Loop Voltage Gain and Phase
Figure 23. Open-Loop Transimpedance Gain
REV. B
-7-
PHASE - Degree
PHASE
-50
AD8004
9 8 7 6 G = +2 RF = 1.21k 5VS
SWING - V p-p
5 4 3 2 1 0 10 100 1000 LOAD RESISTANCE - 10000 +5VS
Figure 24. Short-Term Settling Time
Figure 27. Output Voltage Swing vs. Load
10 9 8
PEAK-TO-PEAK OUTPUT AT CLIPPING POINT - V
G = +2 RF = 1.21k f = 100kHz RL = 1k
7 6
RL = 100 5 4 3 2 1 0 3 4 5 6 7 8 9 10 TOTAL SUPPLY VOLTAGE - V 11 12
Figure 25. Long-Term Settling Time
Figure 28. Output Swing vs. Supply
0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 1ST 2ND 3RD 4TH 5TH 6TH 7TH 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 1ST 2ND 3RD 4TH 5TH 6TH 7TH
0.03
DIFF GAIN - %
DIFF GAIN - %
0.02 0.01 0.00 -0.01 -0.02 -0.03 1ST
80 IRE RL = 150 VS = 5V RF = 1.21k 8TH 9TH 10TH 11TH
80 IRE RL = 1k VS = 5V RF = 1.21k
2ND 3RD 4TH
5TH
6TH
7TH
8TH
9TH 10TH 11TH
DIFF PHASE - Degrees
80 IRE RL = 150 VS = 5V RF = 1.21k 8TH 9TH 10TH 11TH
0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 1ST 2ND 3RD 4TH
DIFF PHASE - Degrees
80 IRE RL = 1k VS = 5V RF = 1.21k 5TH 6TH 7TH 8TH 9TH 10TH 11TH
Figure 26. Differential Gain/Differential Phase
Figure 29. Differential Gain/Phase, RL = 1 k
-8-
REV. B
AD8004
THEORY OF OPERATION
The AD8004 is a member of a new family of high speed currentfeedback (CF) amplifiers offering new levels of bandwidth, distortion, and signal-swing capability vs. power. Its wide dynamic range capabilities are due to both a complementary high speed bipolar process and a new design architecture. The AD8004 is basically a two stage (Figure 30) rather than the conventional one stage design. Both stages feature the current-on-demand property associated with current feedback amplifiers. This gives an unprecedented ratio of quiescent current to dynamic performance. The important properties of slew rate, and full power bandwidth benefit from this performance. In addition the second gain stage buffers the effects of load impedance significantly reducing distortion. A full discussion of this new amplifier architecture is available on the data sheet for the AD8011. This discussion only covers the basic principles of operation.
DC AND AC CHARACTERISTICS
The more exact relationships that take into account open-loop gain errors are:
AV =
G R 1- G 1+ +F AO (s) T O (s) G 1+ R G +F AO (s) T O (s)
for inverting (G is negative)
AV =
for noninverting (G is positive)
As with traditional op amp circuits the dc closed-loop gain is defined as:
R AV = G = 1 + R F N R AV = G = - R F
noninverting operation
In these equations the open-loop voltage gain (AO(s)) is common to both voltage and current-feedback amplifiers and is the ratio of output voltage to differential input voltage. The openloop transimpedance gain (TO(s)) is the ratio of output voltage to inverting input current and is applicable to current-feedback amplifiers. The open-loop voltage gain and open-loop transimpedance gain (TO(s)) of the AD8004 are plotted vs. frequency in Figures 20 and 23. These plots and the basic relationships can be used to predict the first order performance of the AD8004 over frequency. At low closed-loop gains the term (RF /TO(s)) dominates the frequency response characteristics. This gives the result that bandwidth is constant with gain, a familiar property of current feedback amplifiers. An RF of 1 k has been chosen as the nominal value to give optimum frequency response with acceptable peaking at gains of +2/-1. As can be seen from the above relationships, at higher closed-loop gains reducing RF has the effect of increasing closedloop bandwidth. Table I gives optimum values for RF and RG for a variety of gains.
N
inverting operation
A1 IPP CD IPN IQ1 C P1 CP2 VN ZI Q2
IE
A2
Q3 Q1 VP
ICQ + IO V O Z2
A3 RL RF RG CL
VO
Q4 IQ1 A2 INP IPN A1 C P1 CD
AD8004
Figure 30. Simplified Block Diagram
REV. B
-9-
AD8004
DRIVING CAPACITIVE LOADS
The AD8004 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best settling response is obtained by the addition of a small series resistance as shown in Figure 31. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL.
1k
region of the summing junction will cause some bandwidth extension and/or increased peaking. In noninverting gains, the effect of extra capacitance on summing junctions is far more pronounced than versus inverting gains. Figure 34 shows an example of this. Note that only 1 pF of added junction capacitance causes about a 70% bandwidth extension and additional peaking on a gain = +2. For an inverting gain = -2, 5 pF of additional summing junction capacitance caused a small 10% bandwidth extension. Extra output capacitive loading also causes bandwidth extensions and peaking. The effect is more pronounced with less resistive loading from the next stage. Figure 35 shows the effect of direct output capacitive loads for gains of +2 and -2. For both gains CLOAD was set to 10 pF or 0 pF (no extra capacitive loading). For each of the four traces in Figure 35 the resistive loads were 100 . Figure 36 also shows capacitive loading effects only with a lighter output resistive load. Note that even though bandwidth is extended 2x, the flatness dramatically suffers.
+2 RF = 698 +1 G = +1 RF = 1.1k RF = 909 0
RSERIES 1k
AD8004
RL 1k CL
Figure 31. Driving Capacitive Load
40
30
NORMALIZED GAIN - dB, G = +2
+1 G = +2 0 -1 -2 -3 -4 -5 1 VIN = 50mV rms VS = 5V RL = 100 R PACKAGE RF = 1.10k
RF = 604
-2 -3 -4 -5 -6
20
RF = 845
-7 100 -8 500
10
0
5
10 CL - pF
15
20
25
Figure 32. Recommended RSERIES vs. Capacitive Load for 30 ns Settling to 0.1%
OPTIMIZING FLATNESS
10 40 FREQUENCY - MHz
Figure 33. RFEEDBACK vs. Frequency Response, G = +1/+2
+2 0 -2 -4 -6 VIN = 50mV rms RL = 100 5VS -8 CJ = 5.1pF -10 -12 CJ = 0 -10 -12 -14 1 10 40 FREQUENCY - MHz 100 500 -14 NORMALIZED GAIN - dB, G = +2 G = +2 +2 G = -2 NORMALIZED GAIN - dB, G = -2 0 -2 -4 -6 -8 CJ = 1pF CJ = 0
The fine scale gain flatness and -3 dB bandwidth is affected by RFEEDBACK selection as is normal of current feedback amplifiers. With exception of gain = +1, the AD8004 can be adjusted for either maximal flatness with modest closed-loop bandwidth or for mildly peaked-up frequency response with much more bandwidth. Figure 33 shows the effect of three evenly spaced R F changes upon gain = +1 and gain = +2. Table I shows the recommended component values for achieving maximally flat frequency response as well as a faster slightly peaked-up frequency response. Printed circuit board parasitics and device lead frame parasitics also control fine scale gain flatness. The AD8004R package because of its small lead frame offers superior parasitics relative to the N package. In the printed circuit board environment, parasitics such as extra capacitance caused by two parallel and vertical flat conductors on opposite PC board sides in the
Figure 34. Frequency Response vs. Added Summing Junction Capacitance
-10-
REV. B
GAIN - dB, G = +1
-1
RSERIES -
AD8004
+2 0 -2 -4 -6 CL = 10pF VIN = 50mV 5VS RL = 100 -8 -10 CL = 0 -12 -14 NORMALIZED GAIN - dB, G = +2 G = +2, RF = 1.10k +2 NORMALIZED GAIN - dB, G = -2 0 -2 -4 -6 -8 -10 -12 -14 1 10 40 FREQUENCY - MHz 100 500 G = -2, RF = 698 CL = 10pF CL = 0
through R2. This current flows toward the summing junction and requires that the output be 2 V higher than the summing junction or at 3.6 V. When the input is at 1 V, there is 1.2 mA flowing into the summing junction through R3 and 1.2 mA flowing out through R1. These currents balance and leave no current to flow through R2. Thus the output is at the same potential as the inverting input or 1.6 V. The input of the AD876 has a series MOSFET switch that turns on and off at the sampling rate. This MOSFET is connected to a hold capacitor internal to the device. The on impedance of the MOSFET is about 50 , while the hold capacitor is about 5 pF. In a worst case condition, the input voltage to the AD876 will change by a full-scale value (2 V) in one sampling cycle. When the input MOSFET turns on, the output of the op amp will be connected to the charged hold capacitor through the series resistance of the MOSFET. Without any other series resistance, the instantaneous current that flows would be 40 mA. This would cause settling problems for the op amp. The series 100 resistor limits the current that flows instantaneously after the MOSFET turns on to about 13 mA. This resistor cannot be made too large or the high frequency performance will be affected. The sampling MOSFET of the AD876 is closed for only half of each cycle or for 25 ns. Approximately seven time constants are required for settling to 10 bits. The series 100 resistor along with the 50 on resistance and the hold capacitor, create a 750 ps time constant. These values leave a comfortable margin for settling. Obtaining the same results with the op amp A/D combination as compared to driving with a signal generator indicates that the op amp is settling fast enough. Overall the AD8004 provides adequate buffering for the AD876 A/D converter without introducing distortion greater than that of the A/D converter by itself.
+5V R3 1.65k 3.6V 0.1 F 1V 0V VIN 50 R1 499k +3.6V REFT R2 1k
Figure 35. Frequency Response vs. Capacitive Loading, RL = 100 Output
+2 CL = 10pF 0
NORMALIZED GAIN - dB, G = 2
-2 -4 -6 -8 -10 -12 -14
G = +2 RL = 1k 5VS VIN = 50mV rms RF = 1.2k
CL = 0
1
10 40 FREQUENCY - MHz
100
500
Figure 36. Flatness with 10 pF Capacitive Load
DRIVING A SINGLE-SUPPLY A/D CONVERTER
New CMOS A/D converters are placing greater demands on the amplifiers that drive them. Higher resolutions, faster conversion rates and input switching irregularities require superior settling characteristics. In addition, these devices run off a single +5 V supply and consume little power, so good single-supply operation with low power consumption are very important. The AD8004 is well positioned for driving this new class of A/D converters. Figure 37 shows a circuit that uses an AD8004 to drive an AD876, a single supply, 10-bit, 20 MSPS A/D converter that requires only 140 mW. Using the AD8004 for level shifting and driving, the A/D exhibits no degradation in performance compared to when it is driven from a signal generator. The analog input of the AD876 spans 2 V centered at about 2.6 V. The resistor network and bias voltages provide the level shifting and gain required to convert the 0 V to 1 V input signal to a 3.6 V to 1.6 V range that the AD876 wants to see. Biasing the noninverting input of the AD8004 at 1.6 V dc forces the inverting input to be at 1.6 V dc for linear operation of the amplifier. When the input is at 0 V, there is 3.2 mA flowing out of the summing junction via R1 (1.6 V/499 ). R3 has a current of 1.2 mA flowing into the summing junction (3.6 V-1.6 V)/ 1.65 k. The difference of these two currents (2 mA) must flow
0.1 F
10 F
1/4 AD8004
3.6V 0.1 F 1.6V 1.6V
100
AD876
REFB +1.6V
Figure 37. AD8004 Driving the AD876
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8004 requires careful attention to board layout and component selection. Table I shows the recommended component values for the AD8004 and Figures 39-41 show the layout for the AD8004 evaluation boards (14-lead DIP and SOIC). Proper RF design techniques and low parasitic component selection are mandatory.
REV. B
-11-
AD8004
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure 38). One end should be connected to the ground plane and the other within 1/8 in. of each power pin. An additional (4.7 F-10 F) tantalum electrolytic capacitor should be connected in parallel. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance greater than 1 pF at the inverting input will significantly affect high speed performance when operating at low noninverting gains. An example of extra inverting input capacitance can be seen on Figure 35 plot. Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with the proper system characteristic impedance and be properly terminated at each end.
RG RG VIN RT 1/4 C1 0.1 F C2 0.1 F C3 10 F C4 10 F -VS +VS RF RbT, 50 VOUT
INVERTING CONFIGURATION
RF RbT, 50 VOUT 1/4 VIN RT C1 0.1 F C2 0.1 F C3 10 F C4 10 F -VS +VS
NONINVERTING CONFIGURATION
Figure 38. Inverting and Noninverting Configurations
Table I. Recommended Component Values and Typical Bandwidths
Gain AD8004AN (DIP) PACKAGE TYPE RF () RG () RT () Small Signal BW @ 5 VS (MHz) Peaking @ 5 VS 0.1 dB Flatness @ 5 VS (MHz) Small Signal BW @ +5 VS (MHz) AD8004AR (SOIC) PACKAGE TYPE RF () RG () RT () Small Signal BW @ 5 VS (MHz) Peaking @ 5 VS 0.1 dB Flatness @ 5 VS (MHz) Small Signal BW @ +5 VS (MHz) -10 -2 Alternate -2 -1 Alternate -1 +1 Alternate +1 +2 Alternate +2 +10
499 49.9 None 155 < 0.3 dB - 135
698 348 57.6 125 None 25 105
499 249 61.9 180 0.3 dB - 155
649 649 53.6 135 None 30 120
499 499 54.9 190 0.3 dB - 160
1.21 k - 50 150 1.3 dB - 130
806 - 50 250 1.7 dB - 200
1.10 k 1.10 k 50 115 < 0.14 dB 35 95
698 698 50 185 0.4 dB - 150
499 54.9 50 135 < 0.3 dB - 120
499 49.9 None 155 < 0.7 dB - 135
698 348 57.6 130 < 0.1 dB 35 115
499 249 61.9 190 0.5 dB - 175
750 750 53.6 125 None 25 110
499 499 54.9 195 0.4 dB - 165
1.10 k - 50 150 1.3 dB - 130
698 - 50 225 1.8 dB - 195
1.10 k 1.10 k 50 110 < 0.1 dB 30 95
604 604 50 175 0.5 dB - 155
499 54.9 50 135 < 0.2 dB - 120
NOTES 1 RT chosen for 50 characteristic input impedance. 2 Resistor values listed are standard 1% tolerance.
-12-
REV. B
AD8004
Figure 39. Evaluation Board Silkscreen (Top)
REV. B
-13-
AD8004
Figure 40 Evaluation Board Layout (Top Side)
Figure 41. Evaluation Board Layout (Bottom Side, Looking Through the Board)
-14-
REV. B
AD8004
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP (N-14)
14 PIN 1 1 0.795 (20.19) 0.725 (18.42) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 7 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 8 0.280 (7.11) 0.240 (6.10)
0.130 (3.30) MIN SEATING PLANE
0.015 (0.381) 0.008 (0.204)
0.100 (2.54) BSC
0.070 (1.77) 0.045 (1.15)
14-Lead Plastic SOIC (R-14)
0.3444 (8.75) 0.3367 (8.55)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
REV. B
-15-
PRINTED IN U.S.A.
C2078a-0-8/99
-16-
C2078a-0-8/99
PRINTED IN U.S.A.

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